(1) Field of the Invention
The present invention relates to decoding circuits and more particularly to a circuit for eliminating noise when simultaneously decoding a plurality of synchronously generated counter output signals.
(2) Description of the Prior Art
In a fully synchronous binary counter the output signals change state at the same time. However, they do not change instantaneously. Consequently when a signal changes state from a logic 0 to a logic 1, it takes a finite rise time to make such transitions. Similarly when a signal changes state from a logic 1 to a logic 0, it takes a finite fall time for that transition.
When two output signals of a counter are to be decoded simultaneously, noise pulses can be generated if one of the signals changes state from a logic 0 to a logic 1 at the same time that the other signal changes state from a logic 1 to a logic 0. A noise pulse results from this overlap in rise and fall times. If the rise time of one signal is faster then the fall time of the other a noise pulse as wide as the fall time can result. These noise pulses may be detected as logic pulses and thus cause logic errors.
This problem has been solved on the prior art through use of a data verification technique as disclosed in U.S. Pat. No. 4,063,180 to S. R. Norman. However, such a technique which relies on noise detection, requires timing, comparison and gating circuitry. This technique does not eliminate noise but merely adapts to its presence.
Accordingly it is an object of the present invention to provide a novel, low cost, minimum component technique of eliminating noise from a decoding circuit.